A Scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS
A Scalable 0.128–1 Tb/s, 0.8–2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS
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采用 32 nm CMOS 的可扩展 0.128–1 Tb/s、0.8–2.6 pJ/bit、64 通道并行 I/O
DOI：
10.1109/jssc.2013.2279052
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发表时间：
2013
影响因子：
5.4
通讯作者：
B. Casper
中科院分区：
文献类型：
--
作者：
M. Mansuri;J. Jaussi;J. Kennedy;Tzu;S. Shekhar;G. Balamurugan;F. O’Mahony;Clark Roberts;R. Mooney;B. Casper
采用32 nm低功耗CMOS工艺实现了一个可扩展的64通道芯片到芯片I/O，每通道数据速率为2-16 Gb/s。在50 cm通道长度上的最大聚合带宽为1.024 Tb/s时，链路在1.08 V电源下的功耗为2.7 W，相当于2.6 pJ/bit。随着带宽需求的降低，将每通道数据速率扩展到4 Gb/s，电源扩展到0.65 V，可提供最大带宽的1/4，同时消耗0.2 W。在1 m通道上，链路以16 Gb/s的最大每通道数据速率工作;因此，在1.15 V电源下，可提供高达1.024 Tb/s的聚合带宽和3.2 pJ/bit的功率效率。长度匹配的密集互连拓扑允许跨多个通道共享时钟，以减少面积和功耗。可重新配置的电流/电压模式发射器驱动器和CMOS时钟支持高度可扩展的高能效链路。可选的低压差稳压器在200 MHz封装谐振频率下提供>22 dB的电源噪声抑制。跨时钟层次的占空比和正交误差校正器的系统级优化提供了优化的时钟相位布局，从而提高了链路性能和功耗。通道故障转移机制提供设计鲁棒性以减轻通道或电路缺陷。有源电路占用1.3 mm 2。
A scalable 64-lane chip-to-chip I/O, with per-lane data rate of 2-16 Gb/s is demonstrated in 32-nm low-power CMOS technology. At maximum aggregate bandwidth of 1.024 Tb/s across 50-cm channel length, the link consumes 2.7 W from a 1.08-V supply, corresponding to 2.6 pJ/bit. As bandwidth demand decreases, scaling the per-lane data rate to 4 Gb/s and power supply to 0.65 V provides 1/4 of the maximum bandwidth while consuming 0.2 W. Across a 1-m channel, the link operates at a maximum per-lane data rate of 16 Gb/s; thus, providing up to 1.024 Tb/s of aggregate bandwidth with 3.2 pJ/bit power efficiency from a 1.15-V supply. A length-matched dense interconnect topology allows clocking to be shared across multiple lanes to reduce area and power. Reconfigurable current/voltage mode transmitter driver and CMOS clocking enable a highly scalable power-efficient link. Optional low-dropout regulators provide >22-dB supply noise rejection at the package resonance frequency of 200 MHz. System-level optimization of duty-cycle and quadrature error correctors across the clock hierarchy provides optimized clock phase placement and, thus, enhances link performance and power. A lane failover mechanism provides design robustness to mitigate channel or circuit defects. The active circuitry occupies 1.3 mm2.