Characterisation of the NA62 GigaTracker end of column readout ASIC
Characterisation of the NA62 GigaTracker end of column readout ASIC
复制标题
NA62 GigaTracker 列末端读出 ASIC 的特性
DOI：
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
P. Riedler
中科院分区：
文献类型：
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作者：
M. Noy;G. Rinella;M. Fiorini;P. Jarron;J. Kapłon;A. Kluge;E. Martin;M. Morel;L. Perktold;P. Riedler
介绍了用于NA62GigaTracker混合像素探测器的列末演示读出ASIC的结构和特性。该专用集成电路用于1800像素像素芯片的原理证明，该芯片必须执行优于200ps(Rms)的时间戳，提供300GHz m间距位置信息，并且在800μ-1 GHz波束速率下以1%或更小的死区时间工作。演示ASIC包括与其他测试结构并排的具有45个像素的完整测试列。所采用的时间游走校正机制是对超过阈值的时间的测量，并结合探测器外查找表。时间到数字转换器是一个延迟锁定环路，具有32个贡献延迟单元，馈电320 MHz，产生标称面元大小为97 ps。最近，P-in-N传感器已经被凸点连接到ASIC上，并开始对这些组件进行表征。
The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 μm pitch position information and operate with a dead-time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.