MGX: near-zero overhead memory protection for data-intensive accelerators
MGX: near-zero overhead memory protection for data-intensive accelerators
复制标题
DOI：
10.1145/3470496.3527418
复制
发表时间：
2020-04
期刊：
影响因子：
--
通讯作者：
Weizhe Hua;M. Umar;Zhiru Zhang;G. Suh
中科院分区：
文献类型：
--
作者：
Weizhe Hua;M. Umar;Zhiru Zhang;G. Suh
本文介绍了MGX，这是一种用于硬件加速器的接近零高架内存保护方案。 MGX通过利用加速器执行的应用特定属性来最大程度地减少芯片内存加密和完整性验证的性能开销。特别是，加速器倾向于明确管理芯片和片间记忆之间的数据移动。因此，可以在很大程度上确定加速器的一般内存访问模式。利用这些特征，MGX生成了使用芯片加速器状态而不是将它们存储在芯片内存储器中的内存加密和完整性验证中的版本号。它还自定义了记忆保护的粒度，以匹配加速器使用的粒度。为了证明MGX的功效，我们提出了MGX对DNN和图形算法的深入研究。实验结果表明，平均而言，MGX分别在广泛的基准中，DNN和Graph Processing Accelerator的记忆保护性能开销从28％和33％和4％和5％降低。
This paper introduces MGX, a near-zero overhead memory protection scheme for hardware accelerators. MGX minimizes the performance overhead of off-chip memory encryption and integrity verification by exploiting the application-specific properties of the accelerator execution. In particular, accelerators tend to explicitly manage data movement between on-chip and off-chip memories. Therefore, the general memory access pattern of an accelerator can largely be determined for a given application. Exploiting these characteristics, MGX generates version numbers used in memory encryption and integrity verification using on-chip accelerator state rather than storing them in the off-chip memory; it also customizes the granularity of the memory protection to match the granularity used by the accelerator. To demonstrate the efficacy of MGX, we present an in-depth study of MGX for DNN and graph algorithms. Experimental results show that on average, MGX lowers the performance overhead of memory protection from 28% and 33% to 4% and 5% for DNN and graph processing accelerators in a wide range of benchmarks, respectively.