Automatic obfuscated cell layout for trusted split-foundry design
Automatic obfuscated cell layout for trusted split-foundry design
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自动混淆单元布局，实现值得信赖的分体式代工厂设计
DOI：
10.1109/hst.2015.7140237
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发表时间：
2015
期刊：
影响因子：
--
通讯作者：
R. Manohar
中科院分区：
文献类型：
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作者：
Carlos Tadeo Ortega Otero;Jonathan Tse;R. Karmazin;Benjamin Hill;R. Manohar
我们提出了split-cellTK，这是一个自动化混淆分裂铸造布局的工具，其中不可信的铸造厂制造设备（FEOL）和可信的铸造厂完成金属化设计（BEOL）。split-cellTK不会为了混淆而改变设计网表-它接受任意晶体管级网表作为输入。通过混淆FEOL中设备的组织、放置和连接，split-cellTK增加了逆向工程工作的难度。我们评估了两种FEOL混淆方案：均匀布局和随机间距布局。我们扩展了以前在文献中定义的指标集，以捕获在细胞级混淆的好处。我们使用这些指标来评估我们的计划所提供的混淆程度，并提出我们的混淆计划的功率，面积和吞吐量开销。最后，我们提出了测量结果的异步FPGA制造在65 nm的分裂铸造技术，使用我们的工具。
We present split-cellTK, a tool that automates the obfuscation of split-foundry layout, in which an untrusted foundry fabricates the devices (FEOL) and a trusted foundry completes the design with metalization (BEOL). split-cellTK does not alter the design netlist for obfuscation - it accepts an arbitrary transistor-level netlist as input. By obfuscating the the organization, placement and connectivity of devices in the FEOL, split-cellTK increases the difficulty of a reverse engineering effort. We evalute two FEOL obfuscation schemes: uniform layout and layout with random spacing. We extend the set of metrics previously defined in the literature to capture the benefits of obfuscation at the cell level. We use these metrics to evaluate the degree of obfuscation provided by our schemes and present the power, area, and throughput overheads for our obfuscation schemes. Finally, we present measured results for an asynchronous FPGA fabricated in a 65 nm split-foundry technology using our tool.