Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering
Test Clock Domain Optimization to Avoid Scan Shift Failure Due to Flip-Flop Simultaneous Triggering
复制标题
测试时钟域优化以避免由于触发器同时触发而导致扫描移位失败
DOI：
--
复制
发表时间：
2013
影响因子：
2.9
通讯作者：
Hung
中科院分区：
文献类型：
--
作者：
Yu Huang;M. Tsai;Wei;J. Li;M. Chang;Min;C. Tseng;Hung
本文提出了一种可测试性技术的设计，以避免触发器同时触发引起的扫描移位故障。所提出的技术改变了发生严重ir下降问题的触发器的测试时钟域。在优化过程中，采用图形处理器单元的大规模并行算法来加快红外降仿真。大型基准电路的实验数据表明，经过简单MD-SCAN分割后的电路的峰值红外降值平均降低了15%。我们提出的技术在两小时内快速优化了50万个门的设计。
This paper presents a design for testability technique to avoid scan shift failure due to flip-flop simultaneous triggering. The proposed technique changes test clock domains of flip-flops in the regions where severe IR-drop problems occur. A massive parallel algorithm using a graphic processor unit is adopted to speed up the IR-drop simulation during optimization. The experimental data on large benchmark circuits show that peak IR-drop values are reduced by 15% on average compared with the circuit after simple MD-SCAN partition. Our proposed technique quickly optimizes a half-million-gate design within two hours.