Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits
Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits
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DOI：
10.1109/ted.2009.2030831
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发表时间：
2009-11-01
影响因子：
3.1
通讯作者：
Banerjee, Kaustav
中科院分区：
文献类型：
--
作者：
Khatami, Yasin;Banerjee, Kaustav
本文提出了一种新型的基于异质结构Si/本征SiGe沟道层的n型和p型隧道场效应晶体管（T-FET），它具有很小的亚阈值摆幅和很低的阈值电压。根据理论原理和仿真结果，对改善器件特性的设计参数进行了研究和优化。所提出的设备被设计为具有极低的关断电流的数量级为1 fA/μ m和工程表现出显着更高的导通电流相比，以前报道的T-FET器件。这些器件的亚阈值摆幅低至15 mV/dec，阈值电压低至0.13 V。此外，T-FET被设计为表现出与CMOS型数字电路应用兼容的输入和输出特性。使用所提出的n型和p型器件，实现基于T-FET的逆变器电路的报告。将T-FET反相器的性能与65 nm低功耗CMOS反相器进行了比较，T-FET反相器的静态功耗增益接近10（4），门延迟较小。
In this paper, novel n- and p-type tunnel field-effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer are proposed, which exhibit very small subthreshold swings, as well as low threshold voltages. The design parameters for improvement of the characteristics of the devices are studied and optimized based on the theoretical principles and simulation results. The proposed devices are designed to have extremely low OFF currents on the order of 1 fA/mu m and engineered to exhibit substantially higher ON currents compared with previously reported T-FET devices. Subthreshold swings as low as 15 mV/dec and threshold voltages as low as 0.13 V are achieved in these devices. Moreover, the T-FETs are designed to exhibit input and output characteristics compatible with CMOS-type digital-circuit applications. Using the proposed n- and p-type devices, the implementation of an inverter circuit based on T-FETs is reported. The performance of the T-FET-based inverter is compared with the 65-nm low-power CMOS-based inverter, and a gain of similar to 10(4) is achieved in static power consumption for the T-FET-based inverter with smaller gate delay.