A scalable register file architecture for dynamically scheduled processors
A scalable register file architecture for dynamically scheduled processors
复制标题
用于动态调度处理器的可扩展寄存器文件架构
DOI：
10.1109/pact.1996.552666
复制
发表时间：
1996
期刊：
影响因子：
--
通讯作者：
N. Bagherzadeh
中科院分区：
文献类型：
--
作者：
S. Wallace;N. Bagherzadeh
设计动态调度处理器的一个主要障碍是寄存器文件的大小和端口要求。通过使用多组寄存器堆并执行动态结果重命名，可以在不降低性能的情况下实现可扩展的寄存器堆架构。此外，一种新的混合寄存器重命名技术，有效地映射到物理寄存器的逻辑和减少的分支误预测惩罚。使用SPEC95基准套件对性能进行了模拟。
A major obstacle in designing dynamically scheduled processors is the size and port requirement of the register file. By using a multiple banked register file and performing dynamic result renaming, a scalable register file architecture can be implemented without performance degradation. In addition, a new hybrid register renaming technique to efficiently map the logical to physical registers and reduce the branch misprediction penalty is introduced. The performance was simulated using the SPEC95 benchmark suite.