29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS
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29.2 用于 100Gb/s 相干网络的发射器和接收器，具有采用 20nm CMOS 封装的集成 4×64GS/s 8b ADC 和 DAC
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发表时间：
2017
期刊：
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通讯作者：
A. Momtaz
中科院分区：
文献类型：
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作者：
Jun Cao;Delong Cui;A. Nazemi;Tim He;Guansheng Li;B. Çatli;M. Khanpour;Kangmin Hu;Tamer A. Ali;Heng Zhang;Hairong Yu;Ben Rhew;Shiwei Sheng;Y. Shim;Bo Zhang;A. Momtaz
在100Gb/s及以上的速率下，基于CMOS dsp的收发器集成高采样率数据转换器是实现基于相干检测的相敏调制方案的关键，这对于城域和长途网络[1]至关重要。为了支持双极化QPSK格式，需要使用四组低功率dac和adc，并且需要在XI、XQ、YI和YQ通道之间保持精确的相位对准，以传输和提取相干系统中的相位信息，如图29.2.1所示。对于100Gb/s的长途传输，由于FEC开销，每个通道的波特率可高达32Gb/s。此外，接收机通常需要以64GS/s的速度进行双采样，以实现稳健的时钟数据恢复和提高应力信道的信噪比。双采样还使DSP能够在发射端实现更复杂的均衡方案和更灵活的高频频谱工程。本文报道了接收机和发射机完全集成在100G相干DSP芯片上，采用4×64GS/s adc和8b分辨率dac，采用标准20nm CMOS工艺制造。
At rates of 100Gb/s and above, CMOS DSP-based transceivers integrated with high-sampling-rate data converters are critical to realize the phase-sensitive modulation schemes based on coherent detection that are essential to metro and long-haul networks [1]. To support dual-polarization QPSK format, quad low-power DACs and ADCs are needed and precise phase alignment has to be maintained between XI, XQ, YI, and YQ channels, in order to transmit and extract the phase information in the coherent system, as shown in Fig. 29.2.1. For long-haul transmission at 100Gb/s, because of the FEC overhead, the baud rate per channel can be as high as 32Gb/s. In addition, the receiver often requires double sampling at 64GS/s for robust clock-data recovery and SNR improvement for stressed channels. Double sampling also enables the DSP to implement more complicated equalization schemes and more flexible spectrum engineering at high frequency on the transmitter side. This paper reports the receiver and transmitter fully integrated in a 100G coherent DSP chip, using 4×64GS/s ADCs and DACs with 8b resolution, fabricated in a standard 20nm CMOS process.