A single-chip sensor node LSI with synchronous MAC protocol and divided data-buffer SRAM
A single-chip sensor node LSI with synchronous MAC protocol and divided data-buffer SRAM
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DOI：
10.1109/socdc.2009.5423905
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发表时间：
2009-11
期刊：
影响因子：
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通讯作者：
T. Takeuchi;S. Izumi;T. Matsuda;Hyeokjong Lee;T. Konishi;K. Tsuruda;Yasuhiro Sakai;H. Kawaguchi;C. Ohta;M. Yoshimoto
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文献类型：
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作者：
T. Takeuchi;S. Izumi;T. Matsuda;Hyeokjong Lee;T. Konishi;K. Tsuruda;Yasuhiro Sakai;H. Kawaguchi;C. Ohta;M. Yoshimoto
设计了一种超低功耗的无线传感器网络传感器节点VLSI，该芯片采用同步MAC协议和分割数据缓存SRAM。无线传感器网络中最具挑战性的问题之一是延长整个网络的生命周期。因此，引入了以通信为中心的设计方法，通过电路、体系结构和通信协议之间的垂直协同设计来降低射频电路和整个传感器网络系统的功耗。单芯片集成了收发器、i8051微控制器和带分割SRAM的专用MAC处理器。该测试芯片采用180 nm工艺，面积为3.0×1.7 mm2，包括0.63M晶体管。在网络环境下，分块数据缓存平均功耗降低18.6%，功耗为6.34µW。
This paper presents an ultra-low-power singlechip sensor-node VLSI with a synchronous MAC protocol and divided data-buffer SRAM for wireless-sensor-network applications. One of the most challenging issues in wireless sensor networks is extension of the overall network lifetime. So a communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. A transceiver, i8051 microcontroller, and dedicated MAC processor with divided SRAM are integrated in a single chip. The test chip occupies 3.0 × 1.7 mm2 in a 180-nm CMOS process, including 0.63 M transistors. Divided data-buffer reduces 18.6% of average power and the LSI consumes 6.34µW under a network environment.