10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling
10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling
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共同开发的 10 纳米高性能移动 SoC 设计和技术，可实现性能、功耗和面积扩展
DOI：
10.23919/vlsit.2017.7998203
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
Chidambaram
中科院分区：
文献类型：
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作者：
Sam Yang;Yanxiang Liu;M. Cai;Jerry Bao;P. Feng;Xiangdong Chen;L. Ge;Jun Yuan;Jihong Choi;Ping Liu;Youseok Suh;Hao Wang;Jie Deng;Yandong Gao;Jackie Yang;Xiao;Dang;John Zhu;P. Pénzes;SC Song;Chulyong Park;Sungwon Kim;Jedon D. Kim;S. Kang;E. Terzioglu;PR. Chidi Ken Rim;Chidambaram
业界首款10nm低功耗高性能移动SoC成功量产。得益于全面的设计技术合作开发，10nm SoC比其14nm前身快16%，小37%，功耗低30%。最新的SoC具有千兆级调制解调器，旨在推进AR/VR， AJ，机器学习和计算。本文讨论了10nm FinFet技术的扩展挑战，如急剧增加的布线电阻和变化以及强布局应力效应，以说明从技术定义到产品斜坡阶段的设计和技术协同开发是实现扩展权利的必要条件。
The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.