Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics
Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics
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DOI：
10.1038/s41598-019-46186-9
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发表时间：
2019-07-16
影响因子：
4.6
通讯作者：
Wasisto, Hutomo Suryo
中科院分区：
文献类型：
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作者：
Fatahilah, Muhammad Fahlesa;Yu, Feng;Wasisto, Hutomo Suryo
本文报道了基于具有不同NW数（即，1-100）和直径（即，220-640 nm），以证明采用垂直3D架构概念实现大规模并行电子集成的可行性，特别是对于逻辑电路和MEMS应用。一种自顶向下的方法相结合的电感耦合等离子体干法反应离子刻蚀（ICP-DRIE）和湿法化学刻蚀应用于实现垂直对齐的GaN纳米线的金属有机气相外延（MOVPE）为基础的GaN薄膜具有特定的掺杂分布。FET的制造涉及一个n-p-n GaN层的堆栈与嵌入式反向p沟道，顶部漏极桥接接触，和环绕门控技术。从集成NW的电特性，获得（6.6 +/-0.3）V的阈值电压（V-th），这足以安全地在增强模式（E模式）下操作这些器件。通过原子层沉积（ALD）生长的氧化铝（Al 2 O3）被用作栅极电介质材料，导致接近零的栅极滞后（即，-0.2 V的前向和后向扫描第V次移位（Delta V-th））。不管为了具有更好的线性分布而需要的器件处理优化如何，就所产生的电流而言，已经可以证明器件从单个NW到NW阵列的升级能力。因此，所提出的概念有望将微观世界与宏观世界联系起来，并为实现创新的大规模垂直GaN纳米电子学铺平道路。
This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1-100) and diameters (i.e., 220-640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (V-th) of (6.6 +/- 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V-th shift (Delta V-th) of -0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.