Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems
Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems
复制标题
多核实时系统中动态内存带宽调节分析
DOI：
10.1109/rtss.2018.00040
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
G. Fohler
中科院分区：
文献类型：
--
作者：
Ankit Agrawal;R. Mancuso;R. Pellizzoni;G. Fohler
现代多核嵌入式系统中不可预测性的主要来源之一是共享内存资源（例如缓存、互连和DRAM）的争用。尽管在多核系统的设计和分析方面取得了重大成就，但仍需要一个理论框架，当处理器和内存资源都受到调度决策的影响时，该理论框架可用于推理实时工作负载的最坏情况行为。在本文中，我们专注于动态分配的主存带宽。特别是，我们研究了如何确定最坏情况下的响应时间的任务跨越一系列的时间间隔，每个不同的带宽到核心的分配。我们表明，响应时间的计算可以减少到一个最大化问题分配的内存请求到不同的时间间隔，我们提供了一个有效的方法来解决这样的问题。作为一个案例研究，然后，我们展示了如何我们提出的分析可以用来提高集成模块化航空电子系统中存在的内存密集型工作负载的可扩展性。
One of the primary sources of unpredictability in modern multi-core embedded systems is contention over shared memory resources, such as caches, interconnects, and DRAM. Despite significant achievements in the design and analysis of multi-core systems, there is a need for a theoretical framework that can be used to reason on the worst-case behavior of real-time workload when both processors and memory resources are subject to scheduling decisions. In this paper, we focus our attention on dynamic allocation of main memory bandwidth. In particular, we study how to determine the worst-case response time of tasks spanning through a sequence of time intervals, each with a different bandwidth-to-core assignment. We show that the response time computation can be reduced to a maximization problem over assignment of memory requests to different time intervals, and we provide an efficient way to solve such problem. As a case study, we then demonstrate how our proposed analysis can be used to improve the schedulability of Integrated Modular Avionics systems in the presence of memory-intensive workload.
影响因子：
16.6
作者：
Davis, Robert I.;Burns, Alan
通讯作者：
Burns, Alan