Metal–ferroelectric–insulator–Si devices using HfTaO buffer layers
Metal–ferroelectric–insulator–Si devices using HfTaO buffer layers
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DOI：
10.1088/0268-1242/23/4/045002
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发表时间：
2008-04
影响因子：
1.9
通讯作者：
Xubing Lu;K. Maruyama;H. Ishiwara
中科院分区：
文献类型：
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作者：
Xubing Lu;K. Maruyama;H. Ishiwara
采用Pt/Sr0.8Bi2.2Ta2O9（SBT）/HfTaO/Si栅结构制备了金属铁电绝缘体硅（MFIS）二极管和晶体管。HfTaO薄膜在室温下通过电子束蒸发在1.5 × 10 - 9 Torr的背景真空下沉积。通过优化后退火工艺，Al/HfTaO（4 nm）/Si二极管的有效氧化层厚度仅为1.6 nm，在平带电压偏移1 V时的漏电流为2.4 × 10−4 A cm−2，且迟滞回线可忽略不计。采用化学溶液沉积法在HfTaO（4 nm）/Si衬底上沉积SBT薄膜，制备了MFIS二极管。Pt/SBT（300 nm）/HfTaO（4 nm）/Si二极管在+4 V和−4 V之间的电压扫描下获得了0.62 V的存储窗口。使用相同的栅极结构制造了P沟道铁电栅晶体管，其显示出0.6 V的存储窗口和良好的长期保持特性。在固定阅读电压为−0.7 V时，即使经过104 s以上，漏极电流导通/截止比也高达103。
Metal–ferroelectric–insulator–Si (MFIS) diodes and transistors using Pt/Sr0.8Bi2.2Ta2O9 (SBT)/HfTaO/Si gate structures were fabricated. HfTaO films were deposited at room temperature by electron beam evaporation under a background vacuum of ∼1.5 × 10−9 Torr. By process optimization of post-deposition annealing, a small effective oxide thickness of 1.6 nm, a small leakage current of 2.4 × 10−4 A cm−2 at a voltage shifted from the flat band voltage by 1 V and a negligible hysteresis loop were obtained for Al/HfTaO (4 nm)/Si diodes. The MFIS diodes were fabricated by the deposition of SBT films on the HfTaO (4 nm)/Si substrate using chemical solution deposition. A memory window of 0.62 V was obtained for Pt/SBT (300 nm)/HfTaO (4 nm)/Si diodes for a voltage sweep between +4 V and −4 V. P-channel ferroelectric-gate transistors were fabricated using the same gate structure, which showed a memory window of 0.6 V and good long-term retention characteristics. A drain current ON/OFF ratio as high as 103 was attained at a fixed reading voltage of −0.7 V even after over 104 s has elapsed.