Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps
Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps
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DOI：
10.1115/1.4006142
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发表时间：
2012-06
影响因子：
1.6
通讯作者：
K. Nakahira;Hironori Tago;F. Endo;Ken Suzuki;H. Miura
中科院分区：
文献类型：
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作者：
K. Nakahira;Hironori Tago;F. Endo;Ken Suzuki;H. Miura
由于三维集成中的堆叠硅芯片的厚度已经减薄到小于100 μm，由于减薄的芯片的抗弯刚度的降低，芯片的局部热变形急剧增加。由于金属凸块的周期性排列，堆叠芯片中出现明显的周期性热变形，从而出现热残余应力的局部分布，它们有时会降低电子产品的机械和电气可靠性。在本文中，在硅芯片中的局部残余应力的三维有限元分析和测量的结果的基础上，定量研究的主导结构因素的局部残余应力在芯片中使用应力传感器芯片。压阻式应变片嵌入在传感器芯片中。每个应变片的长度为2 μm，一个晶胞由4个不同晶向的应变片组成。这种应变片的排列使我们能够分别测量三维应力场的张量分量。测试倒装芯片基板上的面积阵列锡/铜凸点电镀的硅芯片。凸块的宽度固定为200 μm，凸块间距从400 μm变化到1000 μm。铜凸点的厚度约为40 μm，锡层的厚度约为10 μm。该锡层通过与形成在应力感测芯片上的铜互连合金化而用于形成刚性接头。残余应力的测量幅度从约30 MPa增加到250 MPa，这取决于材料的组合，如凸块，焊料，和互连。结果表明，微凸点的材料常数和微凸点的排列结构是影响微凸点上硅片局部变形和应力的主要因素。它也被证实，不仅是电镀铜薄膜的机械性能的控制，而且通过硅通孔和凸点的犬齿对齐是必不可少的，以最大限度地减少封装引起的应力在三维安装的芯片。该测试芯片对于定量评估三维堆叠芯片中封装工艺引起的应力是非常有效的。
Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper bump was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound’s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process-induced stress in 3D stacked chips quantitatively.