Channel masking synthesis for efficient on-chip test compression
Channel masking synthesis for efficient on-chip test compression
复制标题
用于高效片上测试压缩的通道掩蔽合成
DOI：
10.1109/itc.2004.48
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
B. Keller
中科院分区：
文献类型：
--
作者：
V. Chickermane;Brian Foutz;B. Keller
产品测试压缩方法的有效性因扫描元件捕获未知逻辑状态（“X状态”）而降低。这项工作描述了一种简单但经济高效的解决方案，称为通道屏蔽，它屏蔽 X 状态，并允许测试压缩方法广泛部署在各种设计上。它还讨论了通道屏蔽硬件的各个方面以及支持其在典型设计流程中使用的综合和验证方法。结果显示了其在一些大型工业品外观设计中的有效性。
The effectiveness of on-product test compression methods is degraded by the capture of unknown logic states ("X-states") by the scan elements. This work describes a simple but cost-effective solution called channel masking that masks the X-states and allows test compression methods to be widely deployed on a variety of designs. It also discusses various aspects of the channel masking hardware and the synthesis and validation methodology to support its use in a typical design flow. Results are presented to show its effectiveness on some large industrial designs.