Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults
Variation-Aware Analysis and Test Pattern Generation Based on Functional Faults
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基于功能故障的变化感知分析和测试模式生成
DOI：
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发表时间：
2014
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通讯作者：
M. Fujita
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作者：
M. Fujita
由于半导体技术的不断萎缩，制造芯片的过程中出现了越来越多的变化。从分析芯片功能的角度来看，变化可能会改变芯片的整体“观察”行为。在本文中，我们讨论了额外的延迟所造成的变化，可能会产生变化的观察到的行为。在本文的第一部分中，我们讨论了电路中每个门的输入端上的附加延迟所引起的功能变化。与固定故障不同，这种额外的延迟可以在门上引入许多不同的故障功能。例如，在双输入AND/OR门的情况下，可以潜在地观察到具有双输入的所有可能的逻辑函数，其是222=16个不同的函数。这表明，它可能是有意义的模型的错误行为所造成的变化一般功能故障，而不是结构定义的故障，如固定故障。此外，这种因变化而产生的额外延迟可能会同时发生在多个位置。因此，可以有这么多可能的故障组合被认为是，它是不容易的，在所有与传统的自动测试模式生成（ATPG）的方法，使用显式故障表示故障模拟器下降可检测的故障进行分析。因此，在本文的第二部分，我们讨论了ATPG方法，其中测试向量生成和故障丢弃过程是统一的。由于故障是隐式表示的，即使同时发生的故障数量很大，我们仍然可以成功地执行ATPG过程。
Due to the continuous shrinking of semiconductor technology, there are more and more variations in the process of manufacturing chips. From the viewpoint of analyzing the functionality of a chip, variation may change the overall "observed" behavior of the chip. In this paper, we discuss additional delays caused by variation that may generate changes of observed behaviors. In the first part of the paper, we discuss functional changes caused by additional delays on the inputs of each gate in the circuit. Unlike stuck-at faults, such additional delays can introduce many different faulty functions on a gate. For example, in the cases of two-input AND/OR gate, all possible logic functions with two-input, which are 222=16 different functions, can potentially be observed. This indicates that it may make sense to model faulty behaviors caused by variation as general functional faults rather than structurally defined faults, such as stuck-at faults. Also, such additional delays by variation can happen in multiple locations simultaneously. As a result, there can be so many possible fault combinations to be considered, and it is not easy at all to analyze them with traditional automatic test pattern generation (ATPG) methods which drop detectable faults by fault simulators using explicit representation of faults. So in the second part of the paper, we discuss about ATPG methods where test pattern generation and fault dropping processes are unified. As faults are represented implicitly, even if numbers of simultaneous faults are large, we may still be able to successfully perform ATPG processes.