On the Complexity of Fixed-Size Bit-Vector Logics with Binary Encoded Bit-Width
On the Complexity of Fixed-Size Bit-Vector Logics with Binary Encoded Bit-Width
复制标题
关于二进制编码位宽的固定大小位向量逻辑的复杂性
DOI:
10.29007/cvnz
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发表时间:
2012
影响因子:
3.6
通讯作者:
Armin Biere
中科院分区:
文献类型:
--
作者:
Gergely Kovásznai;Andreas Fröhlich;Armin Biere
Bit-precise reasoning is important for many practical applications of Satisability Modulo Theories (SMT). In recent years ecient approaches for solving xed-size bit-vector formulas have been developed. From the theoretical point of view, only few results on the complexity of xed-size bit-vector logics have been published. In this paper we show that some of these results only hold if unary encoding on the bit-width of bit-vectors is used. We then consider xed-size bit-vector logics with binary encoded bit-width and establish new complexity results. Our proofs show that binary encoding adds more expressiveness to bit-vector logics, e.g. it makes xed-size bit-vector logic even without uninterpreted functions nor quantication NExpTime-complete. We also show that under certain restrictions the increase of complexity when using binary encoding can be avoided.