Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems
Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems
复制标题
90 纳米以下 CMOS 密码系统上基于泄漏的差分功耗分析 (LDPA)
DOI：
10.1109/iscas.2008.4541402
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
W. Burleson
中科院分区：
文献类型：
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作者：
Lang Lin;W. Burleson
由于加密系统在1999年报告了密码系统对差异功率分析（DPA）的脆弱性，因此已经研究了各种功率分析攻击和相应的对策。随着供应电压和CMOS技术的缩小缩小到90 nm以下，泄漏功率在整体功率耗散中起着越来越多的作用。未来的密码系统需要解决这一趋势，尽管在低成本的加密系统（例如智能卡和RFED标签）中尚未关注，这些标签当前使用较旧的技术和低性能晶体管。在本文中，我们探讨了泄漏功率对常规DPA的影响以及新型基于泄漏的DPA（LDPA）的可行性。我们首先使用香料模拟来探讨在90 nm，65 nm和45 nm CMOS技术中实现的逻辑门输入模式的泄漏依赖性。然后，我们在DES密码系统的一个子集上模拟了成功的LDPA，仅120发子弹，与在180 nm技术中报告的200发回合相比之下。此外，我们证明了如何使用耐DPA逻辑样式的DES实施在2000年内与使用5000多个回合的常规DPA相比，在2000发子弹中也可以破坏LDPA。
Since the vulnerability of cryptosystems to differential power analysis (DPA) was reported in 1999, various power analysis attacks and corresponding countermeasures have been studied. With the scaling down of supply voltage and CMOS technology below 90 nm, leakage power plays an increasing role in the overall power dissipation. Future cryptosystems need to address this trend, though it has not been of concern yet in low- cost cryptosystems such as smartcards and RFED tags which currently use older technologies and low performance transistors. In this paper, we explore the impact of leakage power on conventional DPA and the feasibility of a novel leakage-based DPA (LDPA). We first use SPICE simulations to explore the leakage dependence on input patterns of logic gates implemented in 90 nm, 65 nm, and 45 nm CMOS technologies. Then we simulate a successful LDPA on a subset of a DES cryptosystem with only 120 rounds, in contrast to the 200 rounds reported for a conventional DPA in 180 nm technology. Furthermore, we demonstrate how even a DES implementation using a DPA-resistant logic style can be broken with LDPA in 2000 rounds, compared with the conventional DPA using more than 5000 rounds.