SCAMP-3: A Vision Chip with SIMD Current-Mode Analogue Processor Array
SCAMP-3: A Vision Chip with SIMD Current-Mode Analogue Processor Array
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SCAMP-3：具有 SIMD 电流模式模拟处理器阵列的视觉芯片
DOI：
10.1007/978-1-4419-6475-5_2
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
P. Dudek
中科院分区：
文献类型：
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作者：
P. Dudek
本章介绍了具有通用可编程像素并行蜂窝处理器阵列、在单指令多数据（SIMD）模式下运行的视觉芯片的架构、设计和实现。 SIMD 并发处理器架构非常适合实现低级图像处理算法。阵列处理元件的数据路径组件（寄存器、I/O、算术单元）是使用开关电流电路构建的。简单的 SIMD 编程模型与类似数字微处理器的控制和模拟数据路径相结合，产生了易于使用、灵活的系统，具有高度的可编程性以及高效、低功耗、占用空间小的电路实现。 SCAMP-3芯片集成了128×128像素处理器和灵活的读出电路，而控制系统是全数字的，目前在片外实现。该器件在焦平面上实现低级图像处理算法，峰值性能超过20 GOPS，功耗低于240mW。
In this chapter, the architecture, design and implementation of a vision chip with general-purpose programmable pixel-parallel cellular processor array, operating in single instruction multiple data (SIMD) mode is presented. The SIMD concurrent processor architecture is ideally suited to implementing low-level image processing algorithms. The datapath components (registers, I/O, arithmetic unit) of the processing elements of the array are built using switched-current circuits. The combination of a straightforward SIMD programming model, with digital microprocessor-like control and analogue datapath, produces an easy-to-use, flexible system, with high-degree of programmability, and efficient, low-power, small-footprint, circuit implementation. The SCAMP-3 chip integrates 128 ×128 pixel-processors and a flexible read-out circuitry, while the control system is fully digital, and currently implemented off-chip. The device implements low-level image processing algorithms on the focal plane, with a peak performance of more than 20 GOPS, and power consumption below 240mW.
大规模并行模拟视觉处理器上的双目视差计算
DOI：
10.1109/cnna.2010.5430282
发表时间：
2010
期刊：
--
影响因子：
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作者：
Mandai S
通讯作者：
Mandai S