Delay-line temperature sensors and VLSI thermal management demonstrated on a 60nm FPGA
Delay-line temperature sensors and VLSI thermal management demonstrated on a 60nm FPGA
复制标题
在 60nm FPGA 上演示延迟线温度传感器和 VLSI 热管理
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
W. Ng
中科院分区：
文献类型：
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作者：
S. Xie;W. Ng
本文提出了一种基于片上全数字延迟线的温度传感器阵列的热传感和超大规模集成电路热管理方案。提出了一种全数字自校准方法，消除了温度传感器对电源电压和工艺变化的敏感性。提出的校准方法为每个传感器分配一个唯一的校正因子NC，使所有传感器的校准输出在启动时相同。当检测到电源电压变化时，校正因子更新。顺序校准多个基于延迟线的温度传感器只需要一个校准块。对于每个额外的传感器，只需要额外的寄存器来存储NC。所提出的自校准温度传感器在基于Altera Cyclone IV FPGA的VLSI热管理系统上进行了演示。采用混合动态热管理（DTM）方法，得到了四个内核在Cyclone IV FPGA芯片上的运行时热分布图。每个核心在特定温度范围内花费的时间百分比绘制在直方图中。不同DTM技术的比较表明，所提出的混合DTM分别减少了MPSoC在较高温度和较大热梯度下花费的时间，分别减少了10%和21%。此外，与传统的全局DFS方法相比，所提出的混合DTM在平均处理速率（每秒指令数）方面提高了10%。
This paper presents a thermal sensing and VLSI thermal management scheme using an array of on-chip all-digital delay-line based temperature sensors. A fully digital self-calibration method that removes the temperature sensors' sensitivities to supply voltage and process variations is proposed. The proposed calibration method assigns a unique correction factor, NC to each sensor, making all the sensors' calibrated outputs to be the same at start-up. The correction factor is updated when supply voltage variations are detected. Only one calibration block is required to calibrate multiple delay-line based temperature sensors sequentially. For each additional sensor, only additional registers for storing NC are required. The proposed self-calibrated temperature sensors are demonstrated on an Altera Cyclone IV FPGA based VLSI thermal management system. Runtime thermal profiles for four cores mapped on the Cyclone IV FPGA chip using a hybrid dynamic thermal management (DTM) method are obtained. The percentage of time that each core spent in a particular temperature range is plotted in a histogram. A comparison of different DTM techniques demonstrates that the proposed hybrid DTM reduces the amount of time that the MPSoC spent at higher temperatures and larger thermal gradients, by 10% and 21%, respectively. In addition, the proposed hybrid DTM offers a 10% improvement in the average processing rate (instructions per second) when compared with the conventional global DFS approach.