Online Built-In Self-Test of High Switching Frequency DC-DC Converters Using Model Reference Based System Identification Techniques
Online Built-In Self-Test of High Switching Frequency DC-DC Converters Using Model Reference Based System Identification Techniques
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DOI：
10.1109/tcsi.2017.2739479
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发表时间：
2018-02-01
影响因子：
5.1
通讯作者：
Bakkaloglu, Bertan
中科院分区：
文献类型：
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作者：
Beohar, Navankur;Malladi, Venkata N. K.;Bakkaloglu, Bertan
提出了一种内建自测试（BIST）技术，该技术能够在不影响正常工作模式的情况下跟踪集成DC-DC转换器的环路参数。基于数字伪噪声的激励和基于混合信号互相关的分析技术被用于获得片上脉冲响应，与数字相关器方法相比具有最小的计算要求。使用测量的脉冲响应，开环相位裕度和闭环单位增益频率估计在5.2%和4.1%的误差，分别为30 mA至200 mA的负载电流范围。转换器的参数，如自然频率，Q因子，和中心频率估计在3.6%，4.7%，和3.8%的误差，分别为4.7 μ H至10.3 μ H的过负载电感，和200 nF至400 nF的滤波器电容。设计了一个开关频率为5 MHz、输入电压范围为5 V至8.125 V的电压模式控制DC-DC降压转换器，用于基于模型参考的参数和非参数BIST分析。转换器输出电压范围为3.3 V至5 V，支持的最大负载电流为450 mA，峰值效率为87.93%。建议的转换器上制造的0.6 μ m 6层金属SOI技术与9毫米（2）的模具面积。系统识别电路占用3.8%的转换器面积与530 μ A的静态电流在操作过程中。
A built-in self-test (BIST) technique that enables tracking of loop parameters of integrated DC-DC converters without affecting the normal mode of operation is presented. A digital pseudo-noise based stimulus and a mixed signal cross-correlation based analysis technique is used to derive on-chip impulse response, with minimum computational requirements in comparison to a digital correlator approach. Using measured impulse response, open-loop phase margin and closed-loop unity-gain frequency are estimated within 5.2% and 4.1% error, respectively, for the load current range of 30 mA to 200 mA. Converter parameters, such as natural frequency, Q-factor, and center frequency are estimated within 3.6%, 4.7%, and 3.8% error, respectively, over load inductance of 4.7 mu H to 10.3 mu H, and filter capacitance of 200 nF to 400 nF. A 5 MHz switching frequency, 5 V to 8.125 V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed model reference based parametric and non-parametric BIST analysis. The converter output voltage range is 3.3 V to 5 V and supported maximum load current is 450 mA with a peak efficiency of 87.93%. The proposed converter is fabricated on a 0.6 mu m 6 layer-metal SOI technology with a die area of 9 mm(2). The system identification circuitry occupies 3.8% of the converter area with 530 mu A quiescent current during operation.