A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter
A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter
复制标题
具有自主可重构电荷泵和环路滤波器的快速锁定 CDR 电路
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
Suhwan Kim
中科院分区：
文献类型：
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作者：
J. Woo;Hyunjoong Lee;Woo;Heesoo Song;D. Jeong;Suhwan Kim
提出了一种基于锁相环（PLL）的时钟和数据恢复（CDR）电路的设计，以满足快速锁定和低抖动的要求。我们在一个1.25 Gb/s的CDR电路中使用一种新的自主可重构电荷泵和环路滤波器来减少CDR电路的锁定时间。实验样机采用0.18 μ m标准CMOS技术实现。采用我们的CDR电路的接收机的有源面积为380兆赫乘以350兆赫。
This paper presents the design of a phase-locked loop (PLL) based clock and data recovery (CDR) circuit that meets fast locking and low jitter. We reduce the locking time of a CDR circuit using a new autonomously reconfigurable charge pump and loop filter in a 1.25 Gb/s CDR circuit. An experimental prototype was implemented in a 0.18 mum standard CMOS technology. A receiver that incorporates our CDR circuit has an active area of 380 mum times 350 mum.