Hardware architecture and FPGA implementation of a type-2 fuzzy system
Hardware architecture and FPGA implementation of a type-2 fuzzy system
复制标题
2型模糊系统的硬件架构和FPGA实现
DOI：
10.1145/988952.989063
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
C. Peña
中科院分区：
文献类型：
--
作者：
M. Melgarejo;C. Peña
本文提出了一种基于硬件的区间2型模糊推理系统的结构建议。首先，它提出了一个计算模型，考虑并行推理处理和类型约简的基础上计算的内，外边界集。考虑到这一模型，我们设想了一个硬件架构与几个流水线阶段的完全并行执行的类型2模糊推理。该体系结构的建议是用于指定2型模糊处理器与可重构的规则库，这是在FPGA技术实现。实现结果表明，该处理器每秒执行超过30万个类型2模糊推理。
This paper presents an architectural proposal for a hardware-based interval type-2 fuzzy inference system. First, it presents a computational model which considers parallel inference processing and type reduction based on computing inner and outer bound sets. Taking into account this model, we conceived a hardware architecture with several pipeline stages for full parallel execution of type-2 fuzzy inferences. The architectural proposal is used for specifying a type-2 fuzzy processor with reconfigurable rule base, which is implemented over FPGA technology. Implementation results show that this processor performs more than 30 millions of type-2 fuzzy inferences per second.