Modular Routing Design for Chiplet-Based Systems
Modular Routing Design for Chiplet-Based Systems
复制标题
基于 Chiplet 的系统的模块化路由设计
DOI：
--
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
G. Loh
中科院分区：
文献类型：
--
作者：
Jieming Yin;Zhifeng Lin;Onur Kayiran;Matthew Poremba;Muhammad Shoaib Bin Altaf;Natalie D. Enright Jerger;G. Loh
片上系统（SoC）的复杂性和硅成本的增加促使SoC分解成更小的“小芯片”。“基于芯片的SoC设计过程有希望通过使用先进的封装技术来紧密集成多个不同的芯片（例如，CPU、GPU、内存、FPGA）。然而，当将小芯片组装成单个SoC时，正确性验证成为一个重大挑战。特别地，在单个小芯片内和跨小芯片使用的将它们连接在一起的片上网络（NoC）可能容易具有死锁，特别是如果每个芯片被隔离设计。我们介绍了一个简单的，模块化的，但优雅的方法，以确保无死锁路由多芯片系统。作为一个例子，我们专注于未来的系统结合芯片上的有源硅中介层。为了最大化模块化，每个单独的小芯片可以自由地实现其自己的NoC拓扑和本地路由算法，并且中介层可以实现其自己的独立拓扑和路由。我们的方法施加了几个简单的转向限制，只适用于交通，因为它流入或流出的小芯片从中介层，我们提供了一种方法来确定这些限制。最终结果是一种整体方法，可以实现高度模块化的基于芯片的SoC构建，同时消除死锁并实现高性能。
System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking of an SoC into smaller "chiplets." A chiplet-based SoC design process has the promise to enable fast SoC construction by using advanced packaging technologies to tightly integrate multiple disparate chips (e.g., CPU, GPU, memory, FPGA). However, when assembling chiplets into a single SoC, correctness validation becomes a significant challenge. In particular, the network-on-chip (NoC) used within the individual chiplets and across chiplets to tie them together can easily have deadlocks, especially if each chip is designed in isolation. We introduce a simple, modular, yet elegant methodology for ensuring deadlock-free routing in multi-chiplet systems. As an example, we focus on future systems combining chiplets on an active silicon interposer. To maximize modularity, each individual chiplet is free to implement its own NoC topology and local routing algorithm, and the interposer can implement its own independent topology and routing. Our methodology imposes a few simple turn restrictions applied only to traffic as it flows into or out of the chiplets from the interposer, and we provide a way to determine these restrictions. The end result is an overall approach that enables highly-modular, chiplet-based SoC construction while eliminating deadlocks with high performance.