ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors
ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors
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DOI：
10.1109/hpca47549.2020.00034
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发表时间：
2020-02
期刊：
影响因子：
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通讯作者：
Keni Qiu;N. Jao;Mengying Zhao;Cyan Subhra Mishra;Gulsum Gudukbay;Sethu Jose;Jack Sampson;M. Kandemir
中科院分区：
文献类型：
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作者：
Keni Qiu;N. Jao;Mengying Zhao;Cyan Subhra Mishra;Gulsum Gudukbay;Sethu Jose;Jack Sampson;M. Kandemir
最近的许多工作表明，在物联网（IoT）节点上执行推理任务，而不仅仅是传输原始传感器数据，可以大大提高效率。然而，这样的任务，例如，卷积神经网络（CNN）是非常计算密集的。因此，它们在超低功耗和能量收集物联网节点中以传感匹配的方式完成具有挑战性。基于ReRAM交叉杆的加速器（RCA）是在CNN中有效执行占主导地位的乘法和累加（MAC）运算的理想候选者，但是传统的以性能为导向的RCA虽然节能，但对于能量收集物联网节点的间歇性和不稳定的电源来说，功耗很大，并且优化效果不佳。本文介绍了ResiRCA架构，该架构集成了一种新的，轻量级的，可配置的RCA，适用于能量收集环境，作为对基线感测和传输电池供电的物联网节点的机会性执行增强。为了在不同的功率水平下最大限度地提高ResiRCA的吞吐量，我们开发了ResiSchedule方法来进行动态RCA重新配置。所提出的方法使用基于循环平铺的计算分解、RCA内的模型复制和层间流水线来降低RCA激活阈值，并更紧密地跟踪具有动态功率收入的执行成本。实验结果表明，ResiRCA与ResiSchedule一起实现了平均加速比和能源效率分别提高了8倍和14倍，与基线RCA相比，具有容错意识的调度。
Many recent works have shown substantial efficiency boosts from performing inference tasks on Internet of Things (IoT) nodes rather than merely transmitting raw sensor data. However, such tasks, e.g., convolutional neural networks (CNNs), are very compute intensive. They are therefore challenging to complete at sensing-matched latencies in ultra-low-power and energy-harvesting IoT nodes. ReRAM crossbar-based accelerators (RCAs) are an ideal candidate to perform the dominant multiplication-and-accumulation (MAC) operations in CNNs efficiently, but conventional, performance-oriented RCAs, while energy-efficient, are power hungry and ill-optimized for the intermittent and unstable power supply of energy-harvesting IoT nodes. This paper presents the ResiRCA architecture that integrates a new, lightweight, and configurable RCA suitable for energy harvesting environments as an opportunistically executing augmentation to a baseline sense-and-transmit battery-powered IoT node. To maximize ResiRCA throughput under different power levels, we develop the ResiSchedule approach for dynamic RCA reconfiguration. The proposed approach uses loop tiling-based computation decomposition, model duplication within the RCA, and inter-layer pipelining to reduce RCA activation thresholds and more closely track execution costs with dynamic power income. Experimental results show that ResiRCA together with ResiSchedule achieve average speedups and energy efficiency improvements of 8x and 14x respectively compared to a baseline RCA with intermittency-unaware scheduling.