8.1 a 4x4x2 homogeneous scalable 3d network-on-chip circuit with 326mflit/s 0.66pj/b robust and fault-tolerant asynchronous 3d links
8.1 a 4x4x2 homogeneous scalable 3d network-on-chip circuit with 326mflit/s 0.66pj/b robust and fault-tolerant asynchronous 3d links
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8.1 4x4x2 同质可扩展 3D 片上网络电路，具有 326mflit/s 0.66pj/b 稳健且容错的异步 3D 链路
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
J. Michailos
中科院分区：
文献类型：
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作者：
P. Vivet;Y. Thonnart;R. Lemaire;E. Beigné;C. Bernard;F. Darve;D. Lattard;I. Panades;C. Santos;F. Clermidy;S. Chéramy;F. Pétrot;E. Flamand;J. Michailos
通过缩短芯片之间的通信距离，3D技术是持续提高计算密度的关键。对于4G电信基带处理，以常规片上网络（NoC）阵列排列的特定计算单元提供了节能计算[1]。然而，对于高级MIMO处理，当天线的数量增加时，需要更多的计算能力。本文提出了一种均匀的3D电路，由使用4x 4x 2片上网络组装的规则瓦片组成，使用鲁棒和容错的异步3D链路，提供326 MFlit/s@0.66 pJ/B，采用CMOS 65 nm技术，使用1980 TSV以Face 2Back配置制造。
By shortening communication distance across dies, 3D technologies are a key to continued improvements in computing density. For 4G telecom baseband processing, specific computing units arranged in a regular network-on-chip (NoC) array provide power-efficient computation [1]. However, for advanced MIMO processing, more computing power is required when the number of antennas increases. This paper presents a homogeneous 3D circuit composed of regular tiles assembled using a 4x4x2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.