New systolic array implementation of the 2-D discrete cosine transform and its inverse
New systolic array implementation of the 2-D discrete cosine transform and its inverse
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DOI：
10.1109/76.388063
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发表时间：
1995-04
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影响因子：
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通讯作者：
Yu-Tai Chang;Chin-Liang Wang
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文献类型：
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作者：
Yu-Tai Chang;Chin-Liang Wang
提出了一种新的基于行-列分解的二维离散余弦变换（DCT）计算方法，该方法无需矩阵转置硬件。该架构使用N/sup / 2/乘法器以每N个时钟周期一次完整变换的速率计算N/spl次/N点dct，其中N为偶数。它具有规则性和模块化的特点，因此非常适合VLSI的实现。与现有的二维DCT流水线规则架构相比，该架构具有更好的吞吐量性能、更小的区域时间复杂度和更低的通信复杂度。将二维离散余弦变换的新思想扩展到二维离散余弦变换（IDCT）的类似收缩阵列。仿真结果表明，所提出的二维DCT和IDCT结构对真实图像和随机数据都具有良好的不动点误差性能。因此，它们对于需要非常高吞吐率的应用程序非常有用。>
A new systolic array without matrix transposition hardware is proposed to compute the two-dimensional discrete cosine transform (2-D DCT) based on the row-column decomposition. This architecture uses N/sup 2/ multipliers to evaluate N/spl times/N-point DCTs at a rate of one complete transform per N clock cycles, where N is even. It possesses the features of regularity and modularity, and is thus well suited to VLSI implementation. As compared to existing pipelined regular architectures for the 2-D DCT, the proposed one has better throughput performance, smaller area-time complexity, and lower communication complexity. The new idea for the 2-D DCT is also extended to derive a similar systolic array for the 2-D inverse discrete cosine transform (IDCT). Simulation results demonstrate that the proposed 2-D DCT and IDCT architectures have good fixed-point error performance for both real image and random data. As a consequence, they are useful for applications where very high throughput rates are required. >