On Delay Fault Testing in Logic Circuits
On Delay Fault Testing in Logic Circuits
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DOI：
10.1109/tcad.1987.1270315
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发表时间：
1987-09
影响因子：
2.9
通讯作者：
Chin-Jen Lin;S. Reddy
中科院分区：
文献类型：
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作者：
Chin-Jen Lin;S. Reddy
逻辑电路的正确工作要求电路中所有路径的传播延迟小于预期的“时钟间隔”。在正常时钟速率下进行的随机或确定性测试可用于确保制造电路中的路径延迟符合规格。提出了一种基于五值逻辑系统的算法，通过随机延迟测试准确计算路径延迟故障的检测概率，并推导出检测路径延迟故障的确定性测试。当使用随机测试时，结果可用于确定测试路径故障时所需置信水平的测试长度，并且当使用确定性测试时，可用于生成延迟故障列表的测试集。
Correct operation of a logic circuit requires propagation delays of all paths in the circuit to be smaller than the intended "clock interval." Random or deterministic tests, conducted at the normal clocking rate, can be used to insure that path delays in manufactured circuits meet the specifications. Algorithms, based on a five-valued logic system, to accurately calculate the detection probability of path delay faults by random delay tests as well as to derive deterministic tests to detect path delay faults are proposed. The results can be used to determine the test length for a desired confidence level in testing a path fault when random tests are used, and to generate a test set for a list of delay faults when deterministic tests are used.