Binning Optimization for Transparently-Latched Circuits
Binning Optimization for Transparently-Latched Circuits
复制标题
透明锁存电路的分箱优化
DOI：
10.1109/tcad.2010.2081870
复制
发表时间：
2011-02-01
影响因子：
2.9
通讯作者：
Zeng, Xuan
中科院分区：
文献类型：
--
作者：
Gong, Min;Zhou, Hai;Zeng, Xuan
随着工艺变化的不断增加，分形已成为提高芯片制造价值的重要技术，特别是在广泛使用透明锁存器的高性能微处理器中。本文在考虑测试成本的前提下，提出并求解了透明锁存电路中以利润最大化为目标，确定盒边界及其测试顺序的盒优化问题。该问题被分解为四个子问题。首先，为了计算透明锁存电路的时钟周期分布，提出了一种基于样本的统计静态时序分析（SSTA）方法，该方法基于稀疏网格技术的广义随机配置法。通过求解约束图中的最小周期比问题，求出每个采样点上的最小时钟周期。其次，提出了一种贪心方法，通过迭代分配每个边界到其最优位置，在考虑销售收入和测试成本的情况下实现利润最大化；第三，采用基于字母树的O（n log n）运行时间最优算法生成最优测试顺序以最小化测试成本。最后，给出了一种确定最优箱数的简单方法，使整个装箱方案的利润最大化。采用65纳米技术的ISCAS’89系列基准测试显示，平均利润提高10.68%。与其他方法的比较表明了我们方法的优越性。结果还表明，与蒙特卡罗模拟相比，所提出的SSTA方法的误差为0.70%，平均加速为110X。
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the profit (considering the test cost) for a transparently-latched circuit. The problem is decomposed into four sub-problems. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based statistical static timing analysis (SSTA) approach is developed which is based on the generalized stochastic collocation method with the sparse grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy method is proposed to maximize profit considering both the sales revenue and the test cost by iteratively assigning each boundary to its optimal position. Third, an optimal algorithm of O(n log n) runtime is used to generate the optimal testing order to minimize the test cost, based on alphabetic tree. Last, a simple approach is presented to decide the optimal number of bins, which helps to complete the whole binning scheme with maximal profit. Experiments on all the ISCAS'89 sequential benchmarks with 65 nm technology show 10.68% profit improvement in average. Some comparisons with other methods suggest the advantage of our method. The results also demonstrate that the proposed SSTA method achieves an error of 0.70% and speedup of 110X in average compared with the Monte Carlo simulation.