Reducing Solid-State Storage Device Write Stress through Opportunistic In-place Delta Compression
Reducing Solid-State Storage Device Write Stress through Opportunistic In-place Delta Compression
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发表时间：
2016-02
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通讯作者：
Xuebin Zhang;Jiangpeng Li;Hao Wang;Kai Zhao;Tong Zhang
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作者：
Xuebin Zhang;Jiangpeng Li;Hao Wang;Kai Zhao;Tong Zhang
在现代SSD内部，MLC/TLC NAND闪存块的一小部分在SLC模式下操作，以用作写入缓冲器/高速缓存和/或存储热数据。这些SLC模式块吸收了很大比例的写操作。为了平衡存储器磨损，这种MLC/TLC到SLC配置在SSD内的所有存储器块之间旋转。本文提出了一种简单而有效的设计方法，以减少SLC模式闪存块的写压力，从而提高整体SSD的寿命。关键是实现众所周知的增量压缩，而不受传统实践固有的读取延迟和数据管理复杂性的影响。基本的主题是利用SLC模式闪存页面的部分可编程性，以确保原始数据和所有后续增量始终驻留在同一存储器物理页面中。为了避免存储容量开销，我们进一步提出将联合收割机扇区内无损数据压缩与页内增量压缩相结合，从而导致机会性就地增量压缩。本文提出了具体的技术，以解决其实际实现的重要问题，包括数据纠错，和页内数据的放置和管理。我们进行了全面的实验，仿真和ASIC（专用集成电路）设计。结果表明，该设计方案可以在不增加延迟开销的情况下，大大降低SLC模式闪存页面的写压力，同时降低了芯片实现成本。
Inside modern SSDs, a small portion of MLC/TLC NAND flash memory blocks operate in SLC-mode to serve as write buffer/cache and/or store hot data. These SLC-mode blocks absorb a large percentage of write operations. To balance memory wear-out, such MLC/TLC-to-SLC configuration rotates among all the memory blocks inside SSDs. This paper presents a simple yet effective design approach to reduce write stress on SLC-mode flash blocks and hence improve the overall SSD lifetime. The key is to implement well-known delta compression without being subject to the read latency and data management complexity penalties inherent to conventional practice. The underlying theme is to leverage the partial programmability of SLC-mode flash memory pages to ensure that the original data and all the subsequent deltas always reside in the same memory physical page. To avoid the storage capacity overhead, we further propose to combine intra-sector lossless data compression with intra-page delta compression, leading to opportunistic in-place delta compression. This paper presents specific techniques to address important issues for its practical implementation, including data error correction, and intra-page data placement and management. We carried out comprehensive experiments, simulations, and ASIC (application-specific integrated circuit) design. The results show that the proposed design solution can largely reduce the write stress on SLC-mode flash memory pages without significant latency overhead and meanwhile incurs relatively small silicon implementation cost.