High-Speed Modular Multiplier for Lattice-Based Cryptosystems
High-Speed Modular Multiplier for Lattice-Based Cryptosystems
复制标题
用于基于格的密码系统的高速模块化乘法器
DOI：
--
复制
发表时间：
2021
期刊：
影响因子：
--
通讯作者：
Yingjie Lao
中科院分区：
文献类型：
--
作者：
Weihang Tan;Benjamin M. Case;Antian Wang;Shuhong Gao;Yingjie Lao
由于其固有的后量子抗性，基于格的密码学最近在各种密码学应用中受到越来越多的关注。为了便于实际部署，需要高效的硬件架构来加速运算并减少计算资源，特别是多项式乘法，这是基于格的密码系统的瓶颈。在本文中，我们提出了一种用于多项式乘法的新型高速模块化乘法器架构。所提出的架构采用分而治之的策略，并利用特殊的模数来增加并行性并加快计算速度，同时在各种密码系统中实现更广泛的应用。实验结果表明，与之前的工作相比，我们的设计在面积消耗和延迟方面分别减少了约 27% 和 39%。
Thanks to the inherent post-quantum resistant properties, lattice-based cryptography has gained increasing attention in various cryptographic applications recently. To facilitate the practical deployment, efficient hardware architectures are demanded to accelerate the operations and reduce the computational resources, especially for the polynomial multiplication, which is the bottleneck of lattice-based cryptosystems. In this brief, we present a novel high-speed modular multiplier architecture for polynomial multiplication. The proposed architecture employs a divide and conquer strategy and exploits a special modulus to increase the parallelism and speed up the calculation, while enabling wider applications across various cryptosystems. The experimental results show that our design achieves around 27% and 39% reduction on the area consumption and delay, respectively, compared to prior works.