A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise
A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise
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DOI：
10.1109/isscc.2013.6487731
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发表时间：
2013-03
期刊：
影响因子：
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通讯作者：
T. Morie;Takuji Miki;Kazuo Matsukawa;Y. Bando;T. Okumoto;Koji Obata;S. Sakiyama;S. Dosho
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文献类型：
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作者：
T. Morie;Takuji Miki;Kazuo Matsukawa;Y. Bando;T. Okumoto;Koji Obata;S. Sakiyama;S. Dosho
由于SAR-ADC的数字化特性利用了纳米CMOS工艺的高开关速度，因此其功耗效率有所提高。在最近的报告中，时间交织技术和每周期多位转换已经以低功耗将速度提升到GHz采样范围。然而，为了在中等采样速度下实现> 70 dB的SNR，SAR仍然需要大量功率，即数十mW [1-2]。在文献[1]中，通过一个放大残余电荷的级实现了90dB的非常高的SNR，这是在12.5MS/s时功耗为105 mW的原因之一。在文献[2]中，采用8倍过采样和静态电流前置放大器将SNR提高到88 dB，但ADC的功耗仍为66 mW。在文献[3]中，数字校准在3 mW下实现了71 dB的SNDR，但双重转换将采样速度限制为22.5MS/s。本文描述了一种具有71 dB SNDR的SAR ADC，其运行速度为50 MS/s，功耗为4.2mW。该ADC采用3种SNDR增强技术，这些技术利用噪声，并与低压精细数字工艺具有良好的兼容性。
SAR-ADC power efficiency has improved due to its digitally oriented nature that utilizes the high switching speed of nanometer CMOS processes. In recent reports, time-interleaving techniques and multi-bit-per-cycle conversion have boosted speed to the GHz sampling range at low power consumption. However, to achieve SNR of >70dB at moderate sampling speed, SARs still need a lot of power, namely tens of mW [1-2]. In [1], a very high SNR of 90dB is achieved by a stage to amplify residue charge, which is one of the reasons for the 105mW power consumption at 12.5MS/s. In [2], 8× oversampling and a static current pre-amplifier for the comparator improve SNR to 88dB, but the ADC still consumes 66mW. In [3], digital calibration achieves an SNDR of 71dB at 3mW, but double conversion limits the sampling speed to 22.5MS/s.This paper describes a SAR ADC with 71dB SNDR that runs at 50MS/s and consumes 4.2mW. The ADC uses 3 SNDR-enhancement techniques that utilize noise and that have good compatibility to low-voltage fine digital processes.