A real-time, power-efficient architecture for mean-shift image segmentation
A real-time, power-efficient architecture for mean-shift image segmentation
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DOI：
10.1007/s11554-014-0459-1
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发表时间：
2018-02-01
影响因子：
3
通讯作者：
Principe, Jose C.
中科院分区：
文献类型：
--
作者：
Craciun, Stefan;Kirchgessner, Robert;Principe, Jose C.
图像分割对图像处理至关重要，因为它提供了将图像中的对象与背景以及彼此分离的解决方案，这是对象识别，跟踪和其他高级图像处理应用程序的重要步骤。通过将输入图像划分为更小的区域，分割执行提取感兴趣的主要区域（对象和重要特征）的平衡行为，进一步帮助解释图像，同时保持不受无关噪声和不太重要的背景场景的影响。图像分割应用分支到许多领域，从计算机视觉中的决策应用到医学成像和质量控制，仅举几例。mean-shift算法为图像分割提供了一种独特的无监督聚类解决方案，并且对于各种输入图像具有良好的性能记录。然而，mean-shift分割显示出不利的计算复杂度，其中表示像素数和迭代次数。由于这种复杂性，无监督图像分割在需要低功耗、实时解决方案的自动驾驶应用中影响有限。我们提出了一种新的硬件架构，利用fpga的可定制计算能力，并通过并行聚类像素来减少执行时间，同时满足嵌入式应用的低功耗需求。将该架构的性能与现有的CPU和GPU实现进行比较，以证明其在执行时间和能量方面的优势。
Image segmentation is essential to image processing because it provides a solution to the task of separating the objects in an image from the background and from each other, which is an important step in object recognition, tracking, and other high-level image-processing applications. By partitioning the input image into smaller regions, segmentation performs the balancing act of extracting the main areas of interest (objects and important features) that further help to interpret the image, while remaining immune to irrelevant noise and less important background scenes. Image-segmentation applications branch off into a plethora of domains, from decision-making applications in computer vision to medical imaging and quality control to name just a few. The mean-shift algorithm provides a unique unsupervised clustering solution to image segmentation, and it has an established record of good performance for a wide variety of input images. However, mean-shift segmentation exhibits an unfavorable computational complexity of , where represents the number of pixels and the number of iterations. As a result of this complexity, unsupervised image segmentation has had limited impact in autonomous applications, where a low-power, real-time solution is required. We propose a novel hardware architecture that exploits the customizable computing power of FPGAs and reduces the execution time by clustering pixels in parallel while meeting the low-power demands of embedded applications. The architecture performance is compared with existing CPU and GPU implementations to demonstrate its advantages in terms of both execution time and energy.