Reconstruction-Computation-Quantization (RCQ): A Paradigm for Low Bit Width LDPC Decoding
Reconstruction-Computation-Quantization (RCQ): A Paradigm for Low Bit Width LDPC Decoding
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DOI：
10.1109/tcomm.2022.3149913
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发表时间：
2022-04-01
影响因子：
8.3
通讯作者：
Pitchumani, Rekha
中科院分区：
文献类型：
--
作者：
Wang, Linfang;Terrill, Caleb;Pitchumani, Rekha
本文采用重构-计算-量化（RCQ）方法对低密度奇偶校验（LDPC）码进行译码。RCQ有助于动态非均匀量化，以实现具有非常低的消息精度的良好的误帧率（FER）性能。对于根据洪泛调度的消息传递，RCQ参数通过离散密度演化来设计。在IEEE 802.11 LDPC码上的仿真结果表明，对于4比特消息，洪泛最小和RCQ译码器的性能优于信息瓶颈（IB）或Min-IB译码等查表方法，且需要存储的参数显著减少。此外，本文介绍了层特定的RCQ，RCQ解码分层架构的扩展。特定于层的RCQ使用特定于层的消息表示来实现可能的最佳FER性能。针对分层RCQ，本文提出采用分层离散密度演化的分层动态量化（HDQ）的参数设计效率。最后，本文研究了RCQ解码器的现场可编程门阵列（FPGA）实现。对（9472，8192）准循环（QC）LDPC码的仿真结果表明，与5位偏移Min Sum译码器相比，采用3位消息的分层Min Sum RCQ译码器在保持相当译码性能的同时，LUT和路由网减少了10%以上，寄存器使用减少了6%以上。
This paper uses the reconstruction-computation-quantization (RCQ)paradigm to decode low-density parity-check (LDPC) codes. RCQ facilitates dynamic non-uniform quantization to achieve good frame error rate (FER) performance with very low message precision. For message-passing according to a flooding schedule, the RCQ parameters are designed by discrete density evolution. Simulation results on an IEEE 802.11 LDPC code show that for 4-bit messages, a flooding Min Sum RCQ decoder outperforms table-lookup approaches such as information bottleneck (IB) or Min-IB decoding, with significantly fewer parameters to be stored. Additionally, this paper introduces layer-specific RCQ, an extension of RCQ decoding for layered architectures. Layer-specific RCQ uses layer-specific message representations to achieve the best possible FER performance. For layer-specific RCQ, this paper proposes using layered discrete density evolution featuring hierarchical dynamic quantization (HDQ) to design parameters efficiently. Finally, this paper studies field-programmable gate array (FPGA) implementations of RCQ decoders. Simulation results for a (9472, 8192) quasi-cyclic (QC) LDPC code show that a layered Min Sum RCQ decoder with 3-bit messages achieves more than a 10% reduction in LUTs and routed nets and more than a 6% decrease in register usage while maintaining comparable decoding performance, compared to a 5-bit offset Min Sum decoder.