Novel FPGA implementations of Walsh-Hadamard transforms for signal processing
Novel FPGA implementations of Walsh-Hadamard transforms for signal processing
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DOI：
10.1049/ip-vis:20010674
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发表时间：
2001-12-01
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影响因子：
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通讯作者：
Roula, M
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文献类型：
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作者：
Amira, A;Bouridane, A;Roula, M
本文介绍了两种方法适用于现场可编程门阵列（FPGA）实现快速沃尔什-阿达玛变换。这些变换在包括语音压缩、滤波和编码的许多信号处理应用中是重要的。提出了两种新的快速Hadamard变换的结构，它同时使用脉动结构和分布式算法技术。第一种方法使用Baugh-Wooley乘法算法的脉动架构实现。第二种方法是基于分布式算术ROM和累加器结构，和稀疏矩阵分解技术。在Xilinx FPGA板上实现的算法进行了描述。分布式算法的方法表现出更好的性能相比，脉动架构的方法。
The paper describes two approaches suitable for a field-programmable gate-array (FPGA) implementation of fast Walsh-Hadamard transforms. These transforms are important in many signal-processing applications including speech compression, filtering and coding. Two novel architectures for the fast Hadamard transforms using both a systolic architecture and distributed arithmetic techniques are presented. The first approach uses the Baugh-Wooley multiplication algorithm for a systolic architecture implementation. The second approach is based on both a distributed arithmetic ROM and accumulator structure, and a sparse matrix-factorisation technique. Implementations of the algorithms on a Xilinx FPGA board are described. The distributed arithmetic approach exhibits better performances when compared with the systolic architecture approach.