A clockless, multi-stable, CMOS analog circuit
A clockless, multi-stable, CMOS analog circuit
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无时钟、多稳态 CMOS 模拟电路
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
M. Perrott
中科院分区：
文献类型：
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作者：
Mohammad Alhawari;M. Perrott
提出了一种基于阶梯式逆变量化器（LIQAF）电路的CMOS模拟电路拓扑结构，该拓扑结构提供了许多稳定的工作点。当CMOS传输门导通时，输入电压设置初始电压状态值，一旦CMOS传输门关断，电压状态将稳定到最近的稳定工作点。所提出的模拟电路通过一个只需要单一电源电压的电路，通过非线性、连续时间反馈达到其稳定的工作水平。一个集成电路原型演示了该多稳定电路的10电平版本，该电路在0.18μm CMOS中面积为0.015mm2，在1.4V和< 2 v时电流消耗为300μA；为一对多稳定电路提供45μA的1V电源。
A CMOS analog circuit topology is presented that provides a number of stable operating points based on a laddered inverter quantizer (LIQAF) circuit. An input voltage sets the initial voltage state value when a CMOS transmission gate is turned on, and the voltage state then settles to the nearest stable operating point once the CMOS transmission gate is turned off. The proposed analog circuit achieves its stable operating levels through nonlinear, continuous-time feedback with a circuit that requires only a single supply voltage. An IC prototype demonstrates a 10-level version of the multi-stable circuit with an area of 0.015mm2 in 0.18μm CMOS and current consumption of 300μA at 1.4V and <;45μA at 1V supply for a pair of the multi-stable circuits.