GENESIS
GENESIS
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DOI:
10.1145/2629651
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发表时间:
2015-01
期刊:
影响因子:
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通讯作者:
D. Diamantopoulos;K. Siozios;S. Xydis;D. Soudris
中科院分区:
文献类型:
--
作者:
D. Diamantopoulos;K. Siozios;S. Xydis;D. Soudris
Placement is though as the most time-consuming processes in physical implementation flows for reconfigurable architectures, while it highly affects the quality of derived application implementation, as it has impact on the maximum operating frequency. Throughout this article, we propose a novel placer, based on genetic algorithm, targeting to FPGAs. Rather than relevant approaches, which are executed sequentially, the new placer exhibits inherent parallelism, which can benefit from multicore processors. Experimental results prove the effectiveness of this solution, as it achieves average reduction of execution runtime and application’s delay by 67× and 16%, respectively.