An efficient test vector compression scheme using selective huffman coding
An efficient test vector compression scheme using selective huffman coding
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DOI：
10.1109/tcad.2003.811452
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发表时间：
2003-06-01
影响因子：
2.9
通讯作者：
Touba, NA
中科院分区：
文献类型：
--
作者：
Jas, A;Ghosh-Dastidar, J;Touba, NA
本文提出了一种基于选择性霍夫曼编码的压缩/解压缩方案，用于减少制造测试期间必须存储在测试仪上并传输到片上系统 (SOC) 中每个内核的测试数据量。测试仪和 SOC 之间的测试数据带宽是一个瓶颈，在测试包含多个内核的复杂 SOC 时，可能会导致测试时间过长。在所提出的方案中，SOC 的测试向量以压缩形式存储在测试器存储器中，并传输到芯片，在芯片中它们被解压缩并应用于内核。少量片上电路用于解压缩测试向量。给定核心的一组测试向量，仔细选择修改后的霍夫曼代码，使其满足某些属性。这些属性保证了码字可以通过需要非常小的面积的简单流水线解码器（放置在核心扫描链的串行输入处）进行解码。结果表明，所提出的方案可以提供几乎等于最佳霍夫曼码的测试数据压缩，并且解码器的面积开销要少得多。
This paper presents a compression/decompression scheme based on selective Huffman coding for reducing the amount of test data that must be stored on a tester and transferred to each core in a system-on-a-chip (SOC) during manufacturing test. The test data bandwidth between the tester and the SOC is a bottleneck that can result in long test times when testing complex SOCs that contain many cores. In the proposed scheme, the test vectors for the SOC are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the cores. A small amount of on-chip circuitry is used to decompress the test vectors. Given the set of test vectors for a core, a modified Huffman code is carefully selected so that it satisfies certain properties. These properties guarantee that the codewords can be decoded by a simple pipelined decoder (placed at the serial input of the core's scan chain) that requires very small area. Results indicate that the proposed scheme can provide test data compression nearly equal to that of an optimum Huffman code with much less area overhead for the decoder.