A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor
A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor
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DOI：
10.1109/access.2017.2762399
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发表时间：
2017-01-01
期刊：
影响因子：
3.9
通讯作者：
Feng，Songlin
中科院分区：
文献类型：
--
作者：
Huang，Zunkai;Zhang，Xiangyu;Feng，Songlin
高速视觉作为自主车辆和高速跟踪的基础技术，由于资源的限制，一直受到片上带宽和存储瓶颈的困扰。为了提高资源利用率，我们提出了一种基于矢量量化的高速图像传感器的硬件有效的图像压缩电路。在该电路中，自组织映射用于码书的片上学习，以灵活地满足不同应用的要求。为了减少硬件资源，我们提出了一种可重构的完全二进制加法器树，其中的算术单元是完全重用的。此外，采用部分矢量分量存储机制，使压缩比可调。最后，并行基本流设计确保了高处理速度。该电路已在现场可编程门阵列上实现，并应用于高速目标跟踪系统中。实验结果表明，在79.8MHz的工作频率下，该电路在128个权向量下的编码速度达到722帧/s，最大跟踪误差仅为9个像素。这些结果表明，我们提出的电路可以完全集成到高速图像传感器和高速视觉系统中使用。
As the fundamental technology of autonomous vehicles and high-speed tracking, high-speed vision always suffers from the bottlenecks of on-chip bandwidth and storage due to the resource constraints. To improve the resource efficiency, we propose a hardware-efficient image compression circuit based on the vector quantization for a high-speed image sensor. In this circuit, a self-organizing map is implemented for the on-chip learning of codebook to flexibly satisfy the requirements of different applications. To reduce the hardware resources, we present a reconfigurable complete-binary-adder-tree, where the arithmetic units are reused completely. In addition, a mechanism of partial vector-component storage is adapted to make the compression ratio adjustable. Finally, a parallel-elementary-stream design ensures a high processing speed. The proposed circuit has been implemented on the field-programmable gate araray and also applied in a high-speed object tracking system. The experimental results indicate that it achieves an encoding speed of 722 frames/s with 128 weight vectors when working at 79.8 MHz, and the worst tracking error caused by the proposed circuit is merely 9 pixels. These results evince that our proposed circuit can be completely integrated with a high-speed image sensor and used in high-speed vision systems.