A new power efficient high performance interconnection network for many-core processors
A new power efficient high performance interconnection network for many-core processors
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DOI：
10.1016/j.jpdc.2016.11.007
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发表时间：
2017-03-01
影响因子：
3.8
通讯作者：
Inoguchi, Yasushi
中科院分区：
文献类型：
--
作者：
Al Faisal, Faiz;Rahman, M. M. Hafizur;Inoguchi, Yasushi
下一代高性能计算很可能依赖于大规模并行计算机。大规模并行计算机系统的整体性能受互连网络及其处理节点的影响很大。超大规模集成电路技术的持续进步有望为单个节点提供更多的功率。然而，片上互连网络消耗高达50%的总芯片功率，并且片外带宽受限于可能的外出物理链路的最大数量。另外，通信网络的布线长、性能低，大大降低了并行计算机系统的效益，同时也增加了系统的总成本。在本文中，我们提出了一种新的互连网络，减少了高功耗，长布线长度和低带宽的问题。我们已经测量了我们提出的“3D-TESH”互连网络的静态网络性能和所需的功耗，并将其性能与其他网络在不同层次上（如芯片间、节点间和机柜间）进行了比较。3D-TESH网络的直径比3D-Torus网络高出约52.08%，平均距离比3D-Torus网络高出约45.71%，芯片级路由器功耗降低12.61%。此外，3D-TESH在片上级别需要比5D Torus少41%的路由器功耗。(C)2016 Elsevier Inc. All rights reserved.
Next generation high performance computing will most likely depend on the massively parallel computers. The overall performance of a massively parallel computer system is heavily affected by the interconnection network and its processing nodes. Continuing advances in VLSI technologies promise to deliver more power to individual nodes. However, the on-chip interconnection networks consume up to 50% of the total chip power and off-chip bandwidth is limited to the maximum number of possible out going physical links. In addition, the long wiring and low performance of communication network overwhelm the benefit of parallel computer system whereas it increases total cost. In this paper, we propose a new interconnection network that reduces the problems of high power consumption, long wiring length and low bandwidth issues. We have measured the static network performance and required power consumption of our proposed '3D-TESH' interconnection network and compared the performance with other networks at different levels of hierarchy such as inter-chips, inter-nodes and inter-cabinets. 3D-TESH network has achieved about 52.08% better diameter and about 45.71% better average distance than the 3D-Torus network with 12.61% less router power usage at on-chip level. Furthermore, 3D-TESH requires about 41% less router power usage than 5D Torus at the on-chip level. (C) 2016 Elsevier Inc. All rights reserved.