Efficient systolic architecture for Hermitian eigenvalue problem
Efficient systolic architecture for Hermitian eigenvalue problem
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DOI：
10.1109/cwcas.2012.6404064
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发表时间：
2012-11
期刊：
影响因子：
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通讯作者：
A. López-Parrado;Jaime Velasco-Medina
中科院分区：
文献类型：
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作者：
A. López-Parrado;Jaime Velasco-Medina
本文提出了一种有效的收缩期结构，用于解决Hermitian特征值问题，这是WRANS等认知无线电系统的光谱感测功能中的一个常见问题。设计的架构使用一种新型的上三角结构来提高BLV阵列的性能。处理元素基于顺序的线条处理器，以执行两个复杂的雅各比旋转。测试和结果表明，所提出的体系结构适合设计认知无线电系统的频谱感应功能。使用通用结构VHDL描述了收缩期结构，并使用Altera FPGA进行了测试。
This paper presents an efficient systolic architecture for solving the Hermitian eigenvalue problem, which is a common issue in the spectrum sensing function of cognitive radio systems like WRANs. The designed architecture uses a novel upper triangular structure to improve performance with respect to the BLV array. The processing elements are based on sequential CORDIC processors to perform two complex Jacobi rotations. Tests and results show that the proposed architecture is suitable to design the spectrum sensing function of cognitive radio systems. The systolic architecture was described using generic structural VHDL and tested using an Altera FPGA.