Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits
Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits
复制标题
异步 NULL 约定逻辑 (NCL) 电路的测试设计
DOI：
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发表时间：
2008
期刊：
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通讯作者：
S. Kakarla
中科院分区：
文献类型：
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作者：
W. Al;S. Kakarla
由于缺乏全局时钟，并且存在更多同步控制和数据路径的状态保持元素，传统的自动测试模式生成（ATPG）算法在应用于异步电路时失败，导致故障覆盖率低。本文提出了一种流行的异步设计范式的测试设计（DFT）技术，称为NULL约定逻辑（NCL），旨在使用具有合理门开销的现有DFT工具使NCL设计可测试。该技术使用Sandia可控性和可观察性程序（SCOAP）分析执行测试点（tp）插入，以增强反馈网络的可控性和标记为不可观察的故障点的可观察性。开发了自动DFT插入流（ADIF）算法和自定义ATPG NCL原语门库。所开发的DFT技术已在多个NCL基准电路上得到验证
Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using Sandia Controllability and Observability Program (SCOAP) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits