Verified Security for the Morello Capability-enhanced Prototype Arm Architecture
Verified Security for the Morello Capability-enhanced Prototype Arm Architecture
复制标题
Morello 功能增强原型 Arm 架构的安全性经过验证
DOI:
10.1007/978-3-030-99336-8_7
复制
发表时间:
2022
期刊:
影响因子:
--
通讯作者:
Peter Sewell
中科院分区:
文献类型:
--
作者:
Thomas Bauereiß;Brian Campbell;Thomas Sewell;A. Armstrong;Lawrence Esswood;I. Stark;Graeme Barnes;R. Watson;Peter Sewell
, Abstract. Memory safety bugs continue to be a major source of security vulnerabilities in our critical infrastructure. The CHERI project has proposed extending conventional architectures with hardware-supported capabilities to enable fine-grained memory protection and scalable compartmentalisation, allowing historically memory-unsafe C and C++ to be adapted to deterministically mitigate large classes of vulnerabilities, while requiring only minor changes to existing system software sources. Arm is currently designing and building Morello, a CHERI-enabled prototype architecture, processor, SoC, and board, extending the high-per-formance Neoverse N1, to enable industrial evaluation of CHERI and pave the way for potential mass-market adoption. However, for such a major new security-oriented architecture feature, it is important to establish high confidence that it does provide the intended protections, and that cannot be done with conventional engineering techniques. In this paper we put the Morello architecture on a solid mathematical footing from the outset. We define the fundamental security property that Morello aims to provide, reachable capability monotonicity, and prove that the architecture definition satisfies it. This proof is mechanised in Isabelle/HOL, and applies to a translation of the official Arm specification of the Morello instruction-set architecture (ISA) into Isabelle. The main challenge is handling the complexity and scale of a production architecture: 62,000 lines of specification, translated to 210,000 lines of Isabelle. We do so by factoring the proof via a narrow abstraction capturing essential properties of arbitrary CHERI ISAs, the wider CHERI and Morello teams, for their work to make Morello a reality. This work was by the UK Industrial Strategy Challenge Fund (ISCF) the Digital Security by Design (DSbD) Programme, to deliver a DSbDtech enabled digital platform (grant 105694), EPSRC programme grant EP/K008528/1 REMS, ERC AdG 789108 ELVER, Arm iCASE awards, EPSRC IAA KTF funds, the Isaac Newton Trust, the UK Higher Education Innovation Fund (HEIF), Thales E-Security, Microsoft Research Cambridge, Arm, Google, Google DeepMind, HP Enterprise, and the Gates Cambridge Trust. Approved for public release; distribution is unlimited. This work was supported by the Defense Advanced Research Projects Agency (DARPA) and the Research Laboratory (AFRL), under contracts FA8750-10-C-0237 (“CTSRD”), FA8750-11-C-0249 (“MRC2”), HR0011-18-C-0016 (“ECATS”), and FA8650-18-C-7809 (“CIFV”), as part of the DARPA CRASH, MRC, and SSITH research programs. The views, opinions, and/or findings contained in this report are those of the authors and should not be interpreted as representing the official views or policies of the Department of or the U.S. Government.
影响因子:
3.7
作者:
Woodruff J
通讯作者:
Woodruff J
影响因子:
1.8
作者:
Armstrong, Alasdair;Bauereiss, Thomas;Sewell, Peter
通讯作者:
Sewell, Peter
影响因子:
0.8
作者:
Armstrong A
通讯作者:
Armstrong A