Razor: a low-power pipeline based on circuit-level timing speculation
Razor: a low-power pipeline based on circuit-level timing speculation
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Razor：基于电路级时序推测的低功耗管道
DOI：
10.1145/1150343.1150348
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发表时间：
2006
影响因子：
1.5
通讯作者：
T. Austin
中科院分区：
文献类型：
--
作者：
T. Austin
随着时钟频率和芯片集成度的不断提高，功耗感知计算已经成为嵌入式处理器和片上系统设计中的一个关键问题。动态电压缩放（DVS）是一种更有效且广泛使用的功耗感知计算方法。为了从DVS获得最大的省电效果，必须将电源电压调整到尽可能低的水平，同时确保处理器的正确运行。选择临界电压，使得在工艺和环境变化的最坏情况下，处理器总是正确地操作。然而，这种方法导致了一个非常保守的电源电压，因为这种最坏情况下的组合不同的variabilities将是非常罕见的。在这个演讲中，我详细介绍了一种新的方法，DVS，称为剃刀，基于动态检测和校正电路时序误差。Razor的关键思想是通过监控电路运行期间的错误率来调整电源电压，从而消除对电压裕度的需求，并利用电路延迟的数据依赖性。介绍了一种Razor触发器，它对流水线级值进行双采样，一次采用快速时钟，另一次采用时间借用延迟时钟。然后，亚稳态容限比较器验证用快速时钟采样的锁存器值。在定时错误的情况下，修改的流水线误检恢复机制恢复正确的程序状态。将描述原型Razor处理器，沿着物理测量。
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the more effective and widely used methods for power-aware computing is dynamic voltage scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst-case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst-case combination of different variabilities will be very rare.In this talk, I detail a novel approach to DVS, called Razor, based on dynamic detection and correction of circuit timing errors. The key idea of Razor is to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay. A Razor flip-flop is introduced that double-samples pipeline stage values, once with a fast clock and again with a time-borrowing delayed clock. A metastability tolerant comparator then validates latch values sampled with the fast clock. In the event of a timing error, a modified pipeline mispeculation recovery mechanism restores correct program state. A prototype Razor processor will be described, along with physical measurements.