Parallel power grid analysis using distributed direct linear solver

Parallel power grid analysis using distributed direct linear solver
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使用分布式直接线性求解器进行并行电网分析

DOI:
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发表时间:
2014
期刊:
2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)
影响因子:
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通讯作者:
S. Venkateswaran
S. Venkateswaran
中科院分区:
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文献类型:
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作者:
Qing He;W. Au;A. Korobkov;S. Venkateswaran

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准确、高效的电网分析在半导体芯片设计和验证中变得越来越重要。它是高性能处理器设计分析中最具计算挑战性的任务之一。由于存储和操作设计数据所需的内存非常大,因此不再可能在一台计算机上使用一个或多个串行进程来适应分析。本文提出的基于稀疏线性解算器的大规模电网分析方法有效地将计算任务分配到运行在网络内不同计算机上的多个进程上。它为未来的工艺技术和设计世代提供了稳定,准确和可扩展的解决方案。该实现将用于矩阵排序、矩阵分解和解决方案的高级软件包以及消息传递接口(MPI)集成到能够模拟具有数十亿设备的超大规模设计的软件工具中。该方法可以应用于任意大小和配置的电网,并产生类似spice的精度结果。基准分析应用于使用16个分布式进程的最新Sparc处理器设计的最大块,与半导体行业目前采用的最先进的串行解决方案相比,内存利用率提高了6倍以上,性能提高了9倍。
Accurate and efficient power grid analysis has become increasingly important in semiconductors chip design and verification. It is one of the most computationally challenging tasks in high performance processor design analysis. Due to the extremely large memory required to store and manipulate the design data, it is no longer possible to accommodate the analysis using one or more serial processes on a single computer. The proposed method of large scale power grid analysis with sparse linear solver effectively distributes the computing tasks across multiple processes running on different computers within the network. It provides a stable, accurate, and scalable solution for the future process technology and design generations. The implementation incorporates advanced packages for matrix ordering, matrix factorization and solution, and message passing interface (MPI) integrated into the software tool capable of simulating extremely large scale design with billions of devices. The method can be applied to the power grid of arbitrary size and configuration, and produces results with SPICE-like accuracy. The benchmark analysis runs applied to the largest blocks of the latest Sparc processor design using 16 distributed processes demonstrate more than 6X memory utilization improvement and 9X performance improvement over a state-of-the-art serial solution currently employed in semiconductor industry.