A unified compressed memory hierarchy
A unified compressed memory hierarchy
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DOI：
10.1109/hpca.2005.4
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发表时间：
2005-02
期刊：
影响因子：
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通讯作者：
Erik G. Hallnor;S. Reinhardt
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文献类型：
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作者：
Erik G. Hallnor;S. Reinhardt
存储系统对系统性能的巨大且不断增长的贡献促使人们采取更积极的方法来提高其效率。我们提出并分析了一种使用统一压缩方案的存储层次结构，它包括末级片上高速缓存、片外存储通道和片外主存。该方案同时提高了片上有效缓存容量、片外带宽和主存大小，同时避免了不同级别之间的压缩和解压缩开销。使用1MB缓存和128字节块的SPEC CPU2000基准测试的模拟结果显示，平均加速比为19%，而性能下降不超过5%。与单独使用缓存或总线压缩时的165%和83%相比，组合方案的峰值性能提高了292%。当块大小增加到512字节时，压缩系统通常提供更好的性能。
The memory system's large and growing contribution to system performance motivates more aggressive approaches to improving its efficiency. We propose and analyze a memory hierarchy that uses a unified compression scheme encompassing the last-level on-chip cache, the off-chip memory channel, and off-chip main memory. This scheme simultaneously increases the effective on-chip cache capacity, off-chip bandwidth, and main memory size, while avoiding compression and decompression overheads between levels. Simulations of the SPEC CPU2000 benchmarks using a 1MB cache and 128-byte blocks show an average speedup of 19%, while degrading performance by no more than 5%. The combined scheme achieves a peak improvement of 292%, compared to 165% and 83% for cache or bus compression alone. The compressed system generally provides even better performance as the block size is increased to 512 bytes.