Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture
Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture
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研究基于关键性的低功耗处理器架构的功能单元的异构组合
DOI：
10.1145/1071509.1071547
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
Toshinori Sato
中科院分区：
文献类型：
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作者：
A. Chiyonobu;Toshinori Sato
近年来，在便携式和移动的设备上执行需要高处理性能的高级应用。这些设备需要高性能和低功耗的处理器。为了满足这一要求，我们建议利用信息的指令关键性。为了在保持高性能的同时降低能耗，我们的处理器中的每个功能单元都有不同的延迟和能耗。本文描述了基于关键度的低功耗处理器功能单元的最佳组合。评价结果表明，当其功能单元总数为6时，两快四慢组合是最佳的。
In recent years, advanced applications that require high processing performance are executed on portable and mobile devices. Those devices require high-performance and low-power processors. To satisfy this requirement, we propose to exploit information regarding instruction criticality. In order to reduce energy consumption with maintaining high performance, each functional units in our processor has different latency and energy consumption. This paper describes the best combination of functional units for the criticality-based low-power processor. The evaluated results show two fast and four slow combination is the best, when the total number of its functional units is six.