Effects of Basal Plane Dislocations on SiC Power Device Reliability
Effects of Basal Plane Dislocations on SiC Power Device Reliability
复制标题
基面位错对 SiC 功率器件可靠性的影响
DOI：
10.1109/iedm.2018.8614623
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发表时间：
2018
期刊：
影响因子：
--
通讯作者：
R. Green
中科院分区：
文献类型：
--
作者：
R. Stahlbush;K. N. A. Mahakik;A. Lelis;R. Green
随着碳化硅功率器件进入商业电力电子市场，人们对其可靠性的各个方面都产生了浓厚的兴趣。本文讨论了由于基面位错（BPD）引起的MOSFET退化。在MOSFET体二极管的正向偏置期间，电子-空穴复合导致BPD故障，并且在漂移层中产生的堆垛层错使MOSFET劣化。随着层错的增长，MOSFET漂移层的通态电导率降低，漂移层的关态泄漏增加，体二极管的正向电压增加。商用1200 V MOSFET的体电流为5 A或10 A。第一代商用MOSFET在几分钟的应力时间内表现出显著的退化，而最近的MOSFET在超过5小时的应力时间内没有表现出退化。
As silicon carbide power devices enter the commercial power electronics market there is a strong interest in all aspects of their reliability. This work discusses the degradation of MOSFETs due to basal plane dislocations (BPDs). During the forward bias of the MOSFET body diode, electron-hole recombination causes BPDs to fault and the resulting stacking faults in the drift layer degrade the MOSFET. As the stacking faults grow, the on-state conductivity of the MOSFET drift layer decreases, the off-state leakage of the drift layer increases, and the forward voltage of the body diode increases. Commercial 1200 V MOSFETs were stressed with a body current of 5 A or 10 A. The first generation of commercial MOSFETs showed significant degradation within minutes of stress time, whereas more recent MOSFETs did not show degradation for over 5 hours of stress time.