Investigation of Double-Snapback Characteristic in Resistor-Triggered SCRs Stacking Structure
Investigation of Double-Snapback Characteristic in Resistor-Triggered SCRs Stacking Structure
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DOI：
10.1109/ted.2017.2736511
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发表时间：
2017-10
影响因子：
3.1
通讯作者：
S. Yen;Chun‐Hu Cheng;C. Fan;Y. Chiu;H. Hsu;Y. Lan;Chun-Yen Chang
中科院分区：
文献类型：
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作者：
S. Yen;Chun‐Hu Cheng;C. Fan;Y. Chiu;H. Hsu;Y. Lan;Chun-Yen Chang
实现高闩锁抗扰度对于高压（HV）集成电路产品中的电源轨静电放电（ESD）箝位电路至关重要。为了研究并联电阻对电阻触发叠层可控硅（SCR）传输线脉冲电流-电压特性的影响，将横向SCR（LSCR）和改进型LSCR组合成具有不同并联电阻的SCR叠层结构。与传统堆叠式ESD单元相比，SCR的快回裕度不会扩大，甚至可以减小。在0.11 ~\mu \text{m}$32-V的高压工艺中，采用电阻触发叠层SCR技术实现了33.4 V的高保持电压。在该实验中实现了约51 V的触发电压和3.3 A的故障电流。根据基于电压解耦方程的理论分析，采用电阻触发叠层可控硅技术，最小触发电压有可能进一步降低到46 V。本文为电阻触发晶闸管叠层结构ESD保护电路的设计提供了一个简单的指导。
Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current–voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a $0.11~\mu \text{m}$ 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.