Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill
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DOI：
10.1109/tcad.2015.2474365
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发表时间：
2016-03
影响因子：
2.9
通讯作者：
D. Xiang;Kele Shen;B. Bhattacharya;X. Wen;Xijiang Lin
中科院分区：
文献类型：
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作者：
D. Xiang;Kele Shen;B. Bhattacharya;X. Wen;Xijiang Lin
深亚微米或纳米级集成电路（IC）的高速测试消耗过多的功率，并在被测芯片中产生热点和温度梯度。这个问题困扰着3D IC，其中各层之间的散热更不平衡。电路中的这些热点通常会导致性能和可靠性的严重退化，因为温度的升高会沿路径引入额外的延迟沿着。结果，否则无故障路径的延迟可能超过功能时钟周期。因此，这种热紧急情况可能导致测试期间的过度检测和不当的成品率损失。对于小延迟缺陷（SDD），它们的影响将更加严重，其目标是使电路中的长路径敏感。在本文中，我们第一次量化了热紧急情况对SDD的影响，并提供了一种缓解这些影响的解决方案。所提出的方法是基于：1）一个新的热感知（TA）路径选择方法，2）TA测试排序方法，和3）一个有效的扫描架构和测试应用方案。基准测试的实验结果表明，新方法可以显着减少SDD的过检测的数量。
At-speed testing of deep-submicrometer or nano-scale integrated circuits (ICs) consumes excessive power and creates hotspots and temperature gradient in the chip-under-test. The problem worsens for 3-D ICs, where heat dissipation across layers is more unbalanced. These hotspots in a circuit often cause severe degradation of performance and reliability, as a rise in temperature can introduce an extra delay along paths. As a result, the delay of an otherwise fault-free path may exceed the functional clock period. Such thermal emergencies can thus lead to over-detection and undue yield loss during testing. Their effects will be more severe for small-delay defects (SDDs), which target to sensitize the long paths in a circuit. In this paper, we quantify, for the first time, the impact of thermal emergencies on SDDs and provide a solution to mitigate them. The proposed method is based on: 1) a new thermal-aware (TA) path-selection method, 2) a TA test-ordering method, and 3) an effective scan architecture and a test-application scheme. Experimental results on benchmarks demonstrate that the new method can significantly reduce the number of over-detections of SDDs.